1. Field of the Invention
The present invention relates to a method for providing a layout design and a photo mask.
2. Related Art
Layout designs for providing patterns such as contact holes, interconnects or the like of a semiconductor integrated circuit depends upon types of circuits. In a large scale integrated circuit of the standard cell design having a plurality of predetermined logic circuits disposed thereon as unit circuits, a layout design technique of arranging hole patterns of contact holes, via holes and the like at mesh points of orthogonally intersecting virtual grid is employed. The reasons for disposing the hole patterns at the mesh points generally include two reasons.
One reason is that the technique is suitable to be adopted for the automated interconnect layout tool that utilizes a computer aided design (CAD). The interconnects can easily be disposed as originally designed by the circuit utilizing CAD, which executes the processing according to a precedently stored computer program by disposing the cells, the patterned interconnects and the hole patterns at the mesh points designed in accordance with the circuit design.
Another reason is that the technique is to be adopted to a photolithography. The hole patterns are disposed in an array-shape on mesh points, which are intersecting points of the virtual grid having even intervals, when the hole patterns are arranged, so that the photo resist can easily be processed by utilizing interference of light emitted from the adjacent hole patterns in the exposure process to have the hole patterns having the target dimension and shape. In addition, even if the hole patterns are not arranged in an array-shape but if the hole patterns are disposed at the mesh points of the virtual grid, an advantage of enabling an easy generation of the correction shape via an optical proximity correction (OPC) can be obtained.
Needs for achieving the miniaturization and the increased integration of the semiconductor integrated circuits are growing in recent years, and in order to meet the needs, it is recognized that the hole pattern design technique is particularly critical for the photolithography, and the technology of combining a manner of disposing respective hole patterns to points of the virtual grid with a modified illumination method or an use of a phase shift mask is proposed (see, for example, Japanese Patent Laid-Open No. H11-135,402 (1999)).
Next, a layout of a primitive cell that is an unit circuit of a standard cell of a semiconductor integrated circuit will be described.
FIG. 5 is a schematic diagram, showing a layout pattern of a configuration of a primitive cell in a conventional technology. FIG. 5 shows a case of a dual-input NAND gate. This diagram of the primitive cell illustrates the case of dual-input NAND gate having N-type metal oxide semiconductor (MOS) transistor and P-type MOS transistor. Hereinafter, the MOS transistor is merely referred to as “transistor” in the description. In addition, N-type well, P-type well, and N-type diffusion layer and P-type diffusion layer for fixing the well voltages are not illustrated in the figure.
A primitive cell shown in FIG. 5 comprises respective patterns of: a N-type diffusion layer 4 for forming a source region and a drain region of a N-type transistor; a P-type diffusion layer 5 for forming a source region and a drain region of a P-type transistor; a gate electrode 6 of transistor; and a metal interconnect 2 for providing an electrical coupling between devices. A virtual grid 1 generally employed in the typical layout design is designed to have a grid-shape in this layout pattern. Contact holes 3 are arranged on mesh points, which are intersecting points of the orthogonally intersecting lines of the virtual grid 1.
Here, a numeral number 7 indicates a cell bound showing a boundary between the adjacent cells. Hereinafter, an interval of the virtual grid 1 is referred to as a virtual grid size, and a size of n folds of the virtual grid size (n is an integer number) is referred to as a n-virtual grid size.
As shown in FIG. 5, the center-distance between the contact holes 3 that are adjacent across the gate electrode 6 of the P-type transistor is set to the size of the virtual grid. The reason will be described as follows.
Assume that, for example, the size of the contact hole 3 is 0.09 μm×0.09 μm. And concerning the resolution limit pitch, which is the minimum pitch of the resolution limit in an exposure process for semiconductor integrated circuit, assume that the resolution limit pitch of the contact hole 3 is, for example, 0.18 μm. In such case, when the size of the virtual grid is set to 0.18 μm, which is equivalent to the pitch of the resolution limit for the contact hole 3, it is difficult to arrange the contact holes 3 to be mutually adjacent across the gate electrode 6 for ensuring the clearance between the gate electrode 6 and the contact hole 3. When the contact holes are arranged on every other grids with the interval thereof of two meshes of the virtual grid, the contact holes 3 arranged in a relationship of mutually adjacent across the gate electrode 6 are arranged with intervals of 0.36 μm, thereby increasing the flexibility for the layout reference to promote providing larger area thereof. Therefore, as shown in FIG. 5, the contact holes 3 being mutually adjacent across gate electrode 6 may be arranged with a minimum interval that satisfies the associated multiple design reference (for example, 0.27 μm), and the interval between the contact holes 3 can be employed as the virtual grid size to effectively provide reduced cell size.
Next, the photo mask for the exposure process of the contact holes 3 of the primitive cell shown in FIG. 5 will be described.
FIG. 6 is a schematic diagram, showing the photo mask for the exposure process of the contact holes. Here, contact holes 3 shown in FIG. 5 are indicated with numeral number 11 on the photo mask 29.
As shown in the photo mask 29 of FIG. 6, contact holes 11 are arranged at mesh points of the virtual grid 10. In addition, supplementary patterns 12, which are smaller in size than the contact holes 11, are disposed at the mesh points, which are free of the contact holes 11. The size of the supplementary pattern 12 is set to a size that does not provide an opening in the photo resist formed on the wafer by the exposure process for the photo resist, or in other word, a size of being smaller than the resolution limit. In this case, the virtual grid 10 is not formed on the actual photo mask.
Next, the effects obtained by providing the supplementary patterns 12 will be described.
When the contact holes 11 are formed in the photo resist by employing the photo mask that is free of the supplementary pattern 12, the exposure process is conducted under a condition that is suitable for isolated holes, which are contact holes 11 having no adjacent hole of the hole patterns, to form an opening in the isolated holes in the photo resist having an opening size as designed.
However, a size of crowded holes, which have adjacent holes of the hole patterns at all adjacent mesh points, is larger than the targeted size. On the contrary, when the exposure process is conducted under a condition that is adjusted to be suitable for the crowded holes, the opening size of the isolation hole in the photo resist is smaller than the targeted size.
On the other hand, when the supplementary patterns 12 are provided thereon, the optical conditions for the respective holes in the diagrams of the layout pattern shown in FIG. 6 are uniform. Therefore, dimensional change due to a difference in the pattern coarseness and minuteness (proximity effect) is reduced. The reduced proximity effect provides reduced difference in dimensions between the isolated hole and the crowded hole, and thus this results in increasing the flexibility in the required dimension for suitably focusing, thereby promoting the formation of the hole patterns in easier way.
The size of the virtual grid in prior art is set to a dimension that is equal to or larger than the limit interval for providing a resolution to the adjacent contact holes. Alternatively, the size of the virtual grid in prior art may be determined by the other limitations in the design rules than that related to the contact hole, even though the size of the virtual grid is equal to or larger than the pitch for providing a resolution limit. It can be decided by constraint on other design reference except contact hole. Further, in the case of the primitive cell in the standard cell design stated above, the center-distance of the contact holes, which are mutually adjacent across the gate electrode of the transistor, is ordinarily set to the virtual grid size.